Statistical 3D Simulation of Line Edge Roughness in Decanano MOSFETs

Parameter uctuations found in ultrasmall devices are generally associated with discrete random dopants in semiconductors [1,2]. However, dopants are not the only source of intrinsic uctuations in device characteristics that can impede the traditional scaling approach in sub-100 nm MOSFETs. Other stochastic effects, such as oxide thickness uctuations, can also contribute to variations [3]. Line edge roughness (LER), which does not scale with geometry in most types of lithography processes, also introduces intrinsic parameter uctuations and becomes of increasing concern below 100 nm, even in well-scaled devices [4]. Although several workers have investigated the impact of LER in device simulations, these attempts do not account for the true 3D statistical nature of LER. So far all modelling studies have approximated LER in a `square-wave' fashion in deterministic simulations [5,6] or take advantage of faster 2D device simulations in a simplistic statistical approach [7]. We approach the simulation of LER in decanano MOSFETs for the rst time in a truly 3D statistical fashion. LER in our simulations is speci ed in terms of actual statistical parameters, i.e. rms amplitude ( ) and correlation length ( ). This allows both 3D and statistical aspects of LER to be naturally incorparated in a single simulation framework. Data obtained from a variety of processes, as presented in Fig. 1, attest to a minimum total LER limit (3 ) of 5{6 nm, which is larger than the Roadmap requirement for devices below 100 nm [4]. This is alarming, especially given that metrology requirements are often more diÆcult to meet than actual linewidth speci cations for a given process. Less is known regarding the correlation length of LER, which is reported to vary between 10 nm and 50 nm [7]. Our approach to the reconstruction of realistic gate edges is based on a 1D Fourier synthesis approach, assuming a Gaussian or exponential autocorrelation function for the LER. Random line examples generated using this approach are given in Fig. 2 for typical values of and . Such synthesised lines, with correct statistical properties, are used in our 3D simulations to determine source/drain junctions in ensembles of 200 MOSFETs, which have otherwise identical design parameters (Fig. 3). For the sake of simplicity and speed we use the drift-di usion approximation, with constant mobility [12], and neither the quantum mechanical nor the atomistic doping options are enabled during simulations. A set of 200 devices takes 0.5{4 days to run on a single processor depending on the bias conditions, although in practice several processors are used in parallel. This is in marked comparison with 3 months reported for 70 MOSFETs in [7] We study the impact of LER on MOSFETs at several nodes on the SIA roadmap for a range of and values. Speci cally, we focus on the variation of threshold voltage, VT , leakage current, Ioff , and drive current, Ion. Devices considered here comply with scaling requirements at each technology node and assume a Gaussian autocorrelation for LER used to construct the source/drain junction edges. LER causes threshold uctuations similar to those resulting from other stochastic e ects, as can be seen in Fig. 4. Fluctuations increase when rms amplitude is high or when devices are scaled down. The average value of threshold voltage is a ected too, and the magnitude of the uctuations are comparable to those reported for random dopants in similar devices [2]. Several interesting features of our simulations are presented in Fig. 5 to Fig. 8. Leakage current appears to be extremely sensitive to LER in a 30 nm MOSFET. On-current is also a ected, while the ratio of their average value (not shown) increases by 66% in this device. Correlation length dependence of LER saturates at relatively low values of . The current distibutions disclose slight skew, which may be attributed to increased short channel e ects in shorter elements of the ensemble, not to operational asymmetry between source and drain. We will demonstrate how LER may inhibit MOSFET scaling below 50 nm, unless reduced signi cantly both in transverse and lateral directions.